F1 2015 Key Generator


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F1 2015 Key Generator

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F1 2015 Key Generator

This paper presents a new design and verification strategy for Gaussian systemization that supports arbitrary polynomials with nonzero weights up to degree 57, and a new strategy for hardware-based systemization of matrix products and Least Significant Bits (LSBs). Our new approaches allow our key generator to produce a key pair for parameters (m=13), (t=119), and (n=6960) in only 3.7ms when no systemization failure occurs, and in (3.5 ot 3.7)ms on average. To achieve such performance, we implemented an optimized and parameterized Gaussian systemizer for matrix systemization, which works for any large-sized matrix over any binary field ( ext {GF}(2^m)). Our work also presents an FPGA-based implementation of the Gao-Mateer additive FFT, which only takes about 1000 clock cycles to finish the evaluation of a degree-119 polynomial at (2^{13}) data points. The Verilog HDL code of our key generator is parameterized and partly code-generated using Python and Sage. It can be synthesized for different parameters, not just the ones shown in this paper. We tested the design using a Sage reference implementation, iVerilog simulation, and on real FPGA hardware.

We present a new design and verification strategy for Gaussian systemization that supports arbitrary polynomials with nonzero weights up to degree 57, and a new strategy for hardware-based systemization of matrix products and Least Significant Bits (LSBs). Our new approaches allow our key generator to produce a key pair for parameters (m=13), (t=119), and (n=6960) in only 3.7ms when no systemization failure occurs, and in (3.5 ot 3.7)ms on average. To achieve such performance, we implemented an optimized and parameterized Gaussian systemizer for matrix systemization, which works for any large-sized matrix over any binary field ( ext {GF}(2^m)).

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Autore dell'articolo: nepisant

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